? semiconductor components industries, llc, 2007 october, 2007 - rev. 0 1 publication order number: ncp3985/d ncp3985 micropower, 150 ma low-noise, high psrr, ultra-low dropout bicmos voltage regulator the ncp3985 is 150 ma ldo that provides the engineer with a very stable, accurate voltage with low noise and high power supply rejection ratio (psrr) suitable for sensitive applications. in order to optimize performance for battery operated portable applications, the ncp3985 employs an advanced bicmos process to combine the benefits of low noise and superior dynamic performance of bipolar elements with very low ground current consumption at full loads offered by cmos. the ncp3985 is stable with small, low value capacitors and is available in tsop-5 package. features ? output voltage options: - 1.8 v, 2.8 v, 3.0 v - contact factory for other voltage options ? output current limit 200 ma ? low noise (typ 20 v rms ) ? high psrr (typ 70 db) ? stable with ceramic output capacitors as low as 1 f ? low sleep mode current (max 1 a) ? active discharge circuit ? current limit protection ? thermal shutdown protection ? direct replacement for lp3985 ? these are pb-free devices typical applications ? cellular telephones ? noise sensitive applications (video, audio) ? analog power supplies ? pdas / palmtops / organizers / gps ? battery supplied devices ncp3985 ce gnd figure 1. typical application schematic v in v out c in c out c noise v in v out c noise http://onsemi.com marking diagram see detailed ordering, marking and shipping in formation in the package dimensions section on page 8 of this data sheet. ordering information (note: microdot may be in either location) c noise v out gnd v in ce pin assignment (top view) xxx = specific device code a = assembly location y = year w = work week = pb-free package 1 5 xxxayw 1 5 tsop-5 sn suffix case 483
ncp3985 http://onsemi.com 2 figure 2. simplified block diagram + - current limit bandgap reference voltage ce gnd active discharge v out v in c noise pin function description pin no. pin name description 1 v in power supply input voltage 2 gnd power supply ground 3 ce chip enable: this pin allows on/off control of the regulator. to disable the device, connect to gnd. if this function is not in use, connect to v in . internal 5 m pull down resistor is connected between ce and gnd. 4 c noise noise reduction pin. (connect 100 nf or 10 nf capacitor to gnd) 5 v out regulated output voltage maximum ratings rating symbol value unit input voltage (note 1) v in -0.3 v to 6 v v chip enable voltage v ce -0.3 v to v in +0.3 v v noise reduction voltage v cnoise -0.3 v to v in +0.3 v v output voltage v out -0.3 v to v in +0.3 v v maximum junction temperature (note 1) t j(max) 150 c storage temperature range t stg -55 to 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil-std-883, method 3015 machine model method 200 v thermal characteristics rating symbol value unit package thermal resistance: (note 1) junction-to-lead (pin 5) junction-to-ambient r ja 109 220 c/w 1. refer to electrical characteristics and application information for safe operating area
ncp3985 http://onsemi.com 3 electrical characteristics (v in = v out + 1.0 v, v ce = 1.2 v, c in = 0.1 f, c out = 1 f, c noise = 10 nf, t a = -40 c to 85 c , unless otherwise specified (note 2)) characteristic test conditions symbol min typ max unit regulator output input voltage v in 2.5 - 5.5 v output voltage (note 3) 1.8 v 2.8 v 3.0 v v in = (v out +1.0 v) to 5.5 v i out = 1 ma v out 1.764 2.744 2.940 (-2%) - - - 1.836 2.856 3.060 (+2%) v output voltage (note 3) 1.8 v 2.8 v 3.0 v v in = (v out +1.0 v) to 5.5 v i out = 1 ma to 150 ma v out 1.746 2.716 2.910 (-3%) - - - 1.854 2.884 3.090 (+3%) v power supply ripple rejection v in = v out +0.5 v + 0.5 v p-p i out = 1 ma to 150 ma f = 120 hz c noise = 100nf f = 1 khz f = 10 khz psrr - - - 70 70 55 - - - db line regulation v in = (v out +1.0 v) to 5.5 v, i out = 1 ma reg line -0.2 - 0.2 %/v load regulation i out = 1 ma to 150 ma reg load - 12 25 mv output noise voltage f = 10 hz to 100 khz i out = 1 ma to 150 ma c noise = 100 nf c noise = 10 nf v n - - 20 25 - - v rms output current limit v out = v out(nom) C 0.1 v i lim 200 310 470 ma output short circuit current v out = 0 v i sc 210 320 490 ma dropout voltage (note 4) 2.8 v 3.0 v i out = 150 ma v do - - 105 100 155 150 mv general ground current i out = 1 ma i out = 150 ma i gnd - - 70 110 90 220 a disable current v ce = 0 v i dis - 0.1 1.0 a thermal shutdown threshold (note 5) t sd - 150 - c thermal shutdown hysteresis (note 5) t sh - 20 - c chip enable input threshold low high v th(ce) - 1.2 - - 0.4 - v internal pull-down resistance (note 6) r pd(ce) 2.5 5.0 10 m timing turn-on time i out = 150 ma c noise = 10 nf c noise = 100 nf t on - - 0.4 4.0 - - ms turn-off time c noise = 10 nf/100 nf i out = 1 ma i out = 10 ma t off - - 800 200 - - s 2. performance guaranteed over the indicated operating temperature range by design and/ or characterization, production tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible . 3. contact factory for other voltage options. 4. measured when output voltage falls 100 mv below the regulated voltage at v in = v out + 1.0 v if v out < 2.5 v, then v do = v in - v out at v in = 2.5 v. 5. guaranteed by design and characterization. 6. expected to disable device when ce pin is floating.
ncp3985 http://onsemi.com 4 typical characteristics figure 3. output voltage vs. temperature (v out = 1.8 v) figure 4. output voltage vs. temperature (v out = 2.8 v) t a , ambient temperature ( c) t a , ambient temperature ( c) 100 80 60 40 20 0 -20 -40 1.780 1.785 1.790 1.795 1.800 1.810 1.815 1.820 80 60 100 40 20 0 -20 -40 2.780 2.785 2.800 2.795 2.805 2.810 2.815 2.820 figure 5. output voltage vs. temperature (v out = 3.0 v) figure 6. output voltage vs. input voltage t a , ambient temperature ( c) v in , input voltage (v) 100 80 60 40 20 0 -20 -40 2.980 2.985 2.990 2.995 3.000 3.010 3.015 3.020 5 4 3 26 1 0 0 0.5 1.0 1.5 2.0 3.0 3.5 4.0 figure 7. ground current vs. temperature figure 8. ground current vs. input voltage t a , ambient temperature ( c) v in , input voltage (v) 100 80 60 40 20 0 -20 -40 50 60 70 90 100 120 140 6 5 4 3 2 1 0 0 20 40 80 120 140 160 200 v out , output voltage (v) v out , output voltage (v) v out , output voltage (v) v out , output voltage (v) i gnd , ground current ( a) i gnd , ground current ( a) 1.805 i out = 1 ma i out = 150 ma v out = 1.8 v 2.790 i out = 1 ma i out = 150 ma v out = 2.8 v 3.005 i out = 1 ma i out = 150 ma v out = 3.0 v 2.5 i out = 1 ma v out = 3.0 v v out = 2.8 v v out = 1.8 v 80 110 130 i out = 1 ma i out = 150 ma 60 100 180 i out = 1 ma i out = 150 ma v out = 3.0 v v out = 2.8 v v out = 1.8 v 40 t a = 25 c t a = 25 c
ncp3985 http://onsemi.com 5 typical characteristics figure 9. dropout voltage vs. output current figure 10. dropout voltage vs. output current i out , output current (ma) 125 100 75 50 150 25 0 75 80 85 90 100 125 figure 11. current limit vs. temperature figure 12. short circuit current vs. temperature t a , ambient temperature ( c) t a , ambient temperature ( c) 100 80 60 40 20 0 -20 -40 280 300 310 320 330 340 figure 13. psrr vs. frequency figure 14. noise density vs. frequency f, frequency (hz) frequency (hz) 100,000 10,000 1,000 100 10 -100 -90 -80 -70 -40 -30 -10 0 100,000 10,000 1,000 100 10 0 200 400 600 800 1000 1200 1800 v do , dropout voltage (mv) i lim , current limit (ma) i sc , short circuit current limit (ma) psrr (db) v n , noise density (nv/ hz ) t a = 85 c t a = 25 c t a = -40 c v out = 2.8 v 100 80 60 40 20 0 -20 -40 290 300 310 320 340 350 -60 -50 -20 95 105 110 120 115 i out , output current (ma) 125 100 75 50 150 25 0 75 80 85 90 100 125 v do , dropout voltage (mv) t a = 85 c t a = 25 c t a = -40 c v out = 3.0 v 95 105 110 120 115 290 330 t a = 25 c v out = 2.8 v i out = 150 ma c noise = 10 nf t a = 25 c v out = 2.8 v i out = 150 ma c noise = 10 nf 1400 1600
ncp3985 http://onsemi.com 6 typical characteristics figure 15. enable voltage and output voltage vs. time (start-up) figure 16. line transient time (20 s/div) time (100 s/div) figure 17. load transient figure 18. output capacitor esr vs. output current time (40 s/div) i out , output current (ma) 150 125 100 75 50 25 0 0.01 0.1 1 10 esr of output capacitor ( ) v ce 1 v/div v out 1 v/div v in = 4 v i out = 150 ma c noise = 0 nf v out = 1.8 v i out = 150 ma c out = 1 f unstable region stable region v out = 3.0 v v out = 1.8 v i out 100 ma/div v out 50 mv/div v in = 2.8 v v out = 1.8 v c out = 1 f v in 500 mv/div v out 10 mv/div 4.2 v 3.6 v c out = 1 f to 10 f t a = 25 c t a = 25 c t a = 25 c note: typical characteristics were measured with the same conditions as electrical characteristics, unless otherwise noted.
ncp3985 http://onsemi.com 7 application information general the ncp3985 is a 150 ma (current limited) linear regulator with a logic input for on/off control for the high speed turn-off output voltage. access to the major contributor of noise within the integrated circuit is provided as the focus for noise reduction within the linear regulator system. power up/down during power up, the ncp3985 maintains a high impedance output (v out ) until sufficient voltage is present on v in to power the internal bandgap reference voltage. when sufficient voltage is supplied (approx 1.2 v), v out will start to turn on (assume ce shorted to v in ), linearly increasing until the output regulation voltage has been reached. active discharge circuitry has been implemented to insure a fast turn off time. then ce goes low, the active discharge transistor turns on creating a fast discharge of the output voltage. power to drive this circuitry is drawn from the output node. this is to maintain the lowest quiescent current when in the sleep mode (v ce = 0.4 v). this circuitry subsequently turns off when the output voltage discharges. ce (chip enable) the enable function is controller by the logic pin ce. the voltage threshold of this pin is set between 0.4 v and 1.2v. a voltage lower than 0.4 v guarantees the device is off. a voltage higher than 1.2 v guarantees the device is on. the ncp3985 enters a sleep mode when in the off state drawing less than 1 a of quiescent current. the device can be used as a simple regulator without use of the chip enable feature by tying the ce pin to the v in pin. current limit output current is internally limited within the ic to a minimum of 150 ma. the design is set to a higher value to allow for variation in processing and the temperature coefficient of the parameter. the ncp3985 will source this amount of current measured with a voltage 100 mv lower than the typical operating output voltage. the specification for short circuit current limit (@ v out = 0v) is specified at 320 ma (typ). there is no additional circuitry to lower the current limit at low output voltages. this number is provided for informational purposes only. output capacitor the ncp3985 has been designed to work with low esr ceramic capacitors. there is no esr lower lim it for stability for the recommended 1 f output capacitor. stable region for output capacitor esr vs output current is shown in figure18. typical characteristics were measured with murata ceramic capacitors. grm219r71e105k (1 f, 25 v, x7r, 0805) and grm21br71a106k (10 f, 10 v, x7r, 0805). output noise the main contributor for noise present on the output pin v out is the reference voltage node. this is because any noise which is generated at this node will be subsequently amplified through the error amplifier and the pmos pass device. access to the reference voltage node is supplied directly through the c noise pin. noise can be reduced from a typical value of 25 v rms by using 10 nf to 20 v rms by using a 100 nf from the c noise pin to ground. a bypass capacitor is recommended for good noise performance and better load transient response. thermal shutdown when the die temperature exceeds the thermal shutdown threshold, a thermal shutdown (tsd) event is detected and the output (v out ) is turned off. there is no effect from the active discharge circuitry. the ic will remain in this state until the die temperature moves below the shutdown threshold (150 c typical) minus the hysteresis factor (20 c typical). this feature provides protection from a catastrophic device failure due to accidental overheating. it is not intended to be used as a substitute for proper heat sinking. the maximum device power dissipation can be calculated by: p d t j t a r ja thermal resistance value versus copper area and package is shown in figure 19. figure 19. r ja vs. pcb copper area pcb copper area (mm 2 ) 700 600 500 400 300 200 100 0 80 130 180 230 280 330 380 r ja , thermal resistance junction-to-ambient ( c/w) tsop-5 (1 oz) tsop-5 (2 oz)
ncp3985 http://onsemi.com 8 ordering information device nominal output voltage marking package shipping ? ncp3985sn180r2g 1.8 v lka tsop-5 (pb-free) 3000 / tape & reel ncp3985sn280r2g 2.8 v lkb NCP3985SN300R2G 3.0 v lkc ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp3985 http://onsemi.com 9 package dimensions tsop-5 case 483-02 issue h notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. 5. optional construction: an additional trimmed lead is allowed in this location. trimmed lead not to extend more than 0.2 from body. dim min max millimeters a 3.00 bsc b 1.50 bsc c 0.90 1.10 d 0.25 0.50 g 0.95 bsc h 0.01 0.10 j 0.10 0.26 k 0.20 0.60 l 1.25 1.55 m 0 10 s 2.50 3.00 123 54 s a g l b d h c j 0.7 0.028 1.0 0.039 mm inches scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.20 5x c ab t 0.10 2x 2x t 0.20 note 5 t seating plane 0.05 k m detail z detail z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp3985/d the products described herein (ncp3985), may be covered by one or more u.s. patents. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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